1. Field of the Invention
The present invention relates to a semiconductor device and a method of operating the same, and more particularly, to a NAND-type flash memory device and a method of operating the same.
2. Description of the Related Art
Flash memory devices maintain information stored in their memory cells even if their power supply is interrupted. Therefore, flash memory devices are widely used in computers and memory cards.
Flash memory devices are classified as NOR-type flash memory devices and NAND-type flash memory devices. NOR-type flash memory devices have a high sensing margin because they can obtain larger cell current than NAND-type flash memory devices, but they have low integration density. Accordingly, NAND-type flash memory devices are widely used when high integration density is required.
FIG. 1 is a block diagram of a typical NAND-type flash memory device.
Referring to FIG. 1, the NAND-type flash memory device includes a cell array area (C/A) 100 in which a plurality of memory cell transistors are arranged in a matrix. A row decoder (R/D) 300 and a column decoder (C/D) 500, which operate the plurality of memory cell transistors, are disposed around the C/A 100. The C/D 500 includes a sense amplifier (S/A) for amplifying a signal output from the C/A 100. The R/D 300 and the C/D 500 are controlled by an input/output unit (I/O) 700. The I/O 700 processes signals received via a plurality of pads and determines the operation mode, for example, a program mode, an erase mode or a read mode, of the flash memory device. The I/O 700 also outputs signals for selecting desired cells or blocks within the C/A 100. The signals output from the I/O 700 are converted into signals for selecting desired cells or blocks within the C/A 100 by the R/D 300 and the C/D 500. The I/O 700 also has a function of outputting cell information, which is amplified by the S/A in a read mode, to the outside.
FIG. 2 is a circuit diagram partially showing a row decoder and a cell array area, which construct a conventional NAND-type flash memory device. Referring to FIG. 2, a cell array area 100a is composed of a plurality of cell blocks, and each cell block includes a plurality of strings, i.e., m strings S1 through Sm. Each string is interposed between a single bit line BL and a common source line CS. For example, a first string S1 is interposed between a first bit line BL1 and the common source line CS, and an m-th string Sm is interposed between an m-th bit line BLm and the common source line CS. A single string is composed of a single string select transistor SST, a plurality of cell transistors C and a single ground select transistor GST. For example, the first string S1 is composed of a first string select transistor SST1, a first ground select transistor GST1 and n cell transistors C11, C12, C13, . . . , and C1n, which are connected in series between the first string select transistor SST1 and the first ground select transistor GST1. The first string select transistor SST1 is connected to the first bit line BL1, and the first ground select transistor GST1 is connected to the common source line CS. Similarly, the m-th string Sm is composed of an m-th string select transistor SSTm, an m-th ground select transistor GSTm and n cell transistors Cm1, Cm2, Cm3, . . . , and Cmn, which are connected in series between the m-th string select transistor SSTm and the m-th ground select transistor GSTm. The m-th string select transistor SSTm is connected to the m-th bit line BLm, and the m-th ground select transistor GSTm is connected to the common source line CS.
A cell block constructed by the m strings S1 through Sm includes a single string select line SSL, n word lines WL1, WL2, WL3, . . . , and WLn and a single ground select line GSL. The string select line SSL is connected to the gate electrodes of the first through m-th string select transistors SST1 through SSTm. The ground select line GSL is connected to the gate electrodes of the first through m-th ground select transistors GST1 through GSTm. The first word line WL1 is connected to the control gate electrodes of the first cell transistors C11 through Cm1 of the respective strings S1 through Sm. The second word line WL2 is connected to the control gate electrodes of the second cell transistors C12 through Cm2 of the respective strings S1 through Sm. Similarly, the third word line WL3 is connected to the control gate electrodes of the third cell transistors C13 through Cm3, and the n-th word line WLn is connected to the control gate electrode of the n-th cell transistors C1n through Cmn of the respective strings S1 through Sm.
A conventional row decoder 300a includes a single string control line SCL, n word control lines W1, W2, W3, . . . , and Wn, a single ground control line GCL and a plurality of block drivers. A single block driver controls only one cell block. For example, a block driver 310 controls only one cell block which is composed of the first through m-th strings S1 through Sm. The block driver 310 is composed of a single string driver transistor SDT, n word driver transistors WDT1 through WDTn and a single ground driver transistor GDT. The string driver transistor SDT is interposed between the string control line SCL and the string select line SSL, and the ground driver transistor GDT is interposed between the ground control line GCL and the ground select line GSL. The first word driver transistor WDT1 is interposed between the first word control line W1 and the first word line WL1, and the second word driver transistor WDT2 is interposed between the second word control line W2 and the second word line WL2. Similarly, the third word driver transistor WDT3 is interposed between the third word control line W3 and the third word line WL3, and the n-th word driver transistor WDTn is interposed between the n-th word control line Wn and the n-th word line WLn. The block driver 310 also includes a single driver control line DCL which is connected to the gate electrodes of the string driver transistor SDT, the n word driver transistors WDT1 through WDTn and the ground driver transistor GDT.
The following description concerns a method of operating the conventional NAND-type flash memory device of FIG. 2.
When a desired cell transistor, for example, the second cell transistor C12 of the first string S1, in the cell array area 100a is intended to be selectively programmed, a voltage of 0 volts is applied to a semiconductor substrate with the cell array area 100a, that is, to the bulk areas of the cell transistors and the common source line CS. In addition, a voltage of 0 volts is applied to the first bit line BL1 connected to the first string S1 and the ground control line GCL. In this case, a program inhibition Vpi, for example, a power voltage Vcc, is applied to the second through m-th bit lines BL2, . . . , BLm, i.e., the unselected bit lines. A power voltage Vcc is applied to the string control line SCL, and a program voltage VPGM of about 20 volts is applied to the second word control line W2. A voltage of 0 volts is applied to the first and third word control lines W1 and W3, and a pass voltage VPASS of about 11 volts is applied to the fourth through n-th word control lines W4, . . . , Wn. A voltage, which is higher than the program voltage VPGM applied to the second word control line W2, i.e., a voltage of VPGM+xcex1, is applied to the driver control line DCL to completely turn on the second word driver transistor WDT2. Here, the voltage xcex1 must be higher than the threshold voltage of the second word driver transistor WDT2.
As described above, to program the conventional NAND-type flash memory device, a high voltage higher than a program voltage should be applied to the driver control line DCL of the block driver 310 for controlling the selected cell block. As a result, the string driver transistor SDT, n word driver transistors WDT1, WDT2, . . . , and WDTn and the ground driver transistor GDT are all turned on. At this time, the selected second cell transistor C12 is programmed by F-N tunneling current, and the unselected cell transistors are inhibited from being programmed by a self-boosting phenomenon [Tae-Sung Jung, et. al. xe2x80x9cA 3.3 V 128 Mb Multi-Level NAND Flash Memory for Mass Storage Applicationxe2x80x9d, ISSCC Digest of Technology Papers, pp. 32-33, Feb., 1996].
FIG. 3 is a sectional view showing the condition of a bias, which is applied to the first and third word driver transistors WDT1 and WDT3 and the ground driver transistor GDT when the second cell transistor C12 of the first string S1 is selectively programmed. Referring to FIG. 3, a voltage of VPGM+xcex1 is applied to the gate electrodes 7 of the first and third word driver transistors WDT1 and WDT3 and the ground driver transistors GDT, and a voltage of 0 volts is applied to source/drain regions 3 and bulk region 1. As a result, a channel region 9 of 0 volts is formed on the surface of the bulk region 1 between the source/drain regions 3. Consequently, a high electric field caused by the voltage of VPGM+xcex1 is applied to a gate insulating film 5, thereby deteriorating the reliability of the gate insulating film 5.
FIG. 4 is a graph showing the results of measuring the reliability of the driver transistors SDT, WDT1, . . . , WDTn and GDT. The horizontal axis indicates the number N of applications of an electrical stress, that is, a pulse signal having a voltage of 25 volts and a width of 1.5 msec, to the gate electrode of each of the driver transistors SDT, WDT1, . . . , WDTn and GDT. The vertical axis indicates the threshold voltage of each of the driver transistors SDT, WDT1 , . . . , WDTn and GDT. At this time, a voltage of 0 volts was applied to all the bulk regions and the source/drain regions in the driver transistors SDT, WDT1, . . . , WDTn and GDT. The electrical stress was applied in an atmosphere having a temperature of 85xc2x0 C. In FIG. 4, data referred to as a is a result of measuring the reliability of driver transistors having a gate insulating film which is formed of a thermal oxide film having a thickness of 330 xc3x85, and data referred to as b is a result of measuring the reliability of driver transistors having a gate insulating film which is formed of a thermal oxide film having a thickness of 300 xc3x85.
It can be seen from FIG. 4 that the threshold voltage of a driver transistor gradually decreases as the number of applications of a high voltage of about 25 volts to the gate electrode of the driver transistor increases. In addition, it can be seen that the reliability of a driver transistor decreases as the thickness of the gate insulating film of the driver transistor decreases. Therefore, a program voltage should be lowered or the thickness of the gate insulating film of a driver transistor should be increased, to prevent the deterioration of the reliability of the driver transistor. However, due to a coupling ratio related to an inter-gate dielectric film, which is interposed between a floating gate and a control gate electrode in a cell transistor, and to a tunnel oxide film, which is interposed between the floating gate and a semiconductor substrate, it is difficult to decrease a program voltage. Moreover, when thickly forming the gate insulating film of a driver transistor, an additional process is required, thereby complicating fabrication processes.
As described above, when the threshold voltage of a driver transistor is lowered, the sub-threshold characteristic of the driver transistor deteriorates. Accordingly, even if a voltage of 0 volts is applied to the gate electrode, leakage current flows between the source region and the drain region. In the case where the sub-threshold characteristics of the driver transistors, particularly, the word driver transistors, deteriorate, a problem of erasing unselected cell blocks may occur when a selected cell block is erased in a NAND-type flash memory device.
With reference back to FIG. 2, the erasing operation of a conventional NAND-type flash memory device will be described. It is assumed that a selected cell block to be erased is a certain cell block (not shown) which has the same structure as the cell block including the first through m-th strings S1 through Sm and shares the m bit lines BL1 through BLm. Accordingly, the cell block including the first through m-th strings S1 through Sm is not selected. The selected cell block is controlled by an additional block driver (not shown) which has the same structure as the block driver 310 of FIG. 2, as described above.
To erase only the selected cell block, the m bit lines BL1 through BLm are floated, and an erase voltage VERASE of about 20 volts is applied to a semiconductor substrate on which the cell array area 100a is formed, that is, the bulk regions of the cell transistors of the selected and unselected cell blocks. All common source lines CS are floated. The common source lines CS may be electrically connected to the bulk regions. In this case, the same erase voltage VERASE applied to the bulk regions is applied to the common source line CS. In addition, the string control line SCL and the ground control line GCL are floated, and a voltage of 0 volts is applied to the first through n-th word control lines W1, W2, W3, . . . , and Wn. A power voltage Vcc is applied to the driver control line of the block driver which controls the selected cell block to turn on all the driver transistors of the selected block driver. On the other hand, a voltage of 0 volts is applied to the driver control line DCL of the block driver 310 which controls the unselected cell block to turn off all the driver transistors SDT, WDT1, WDT2, WDT3, . . . , WDTn and GDT of the unselected block driver 310.
As described above, when an appropriate voltage is applied to each control line, a voltage of 0 volts is applied to the control gate electrodes of all cell transistors within the selected cell block. Accordingly, holes from the bulk regions are injected into the floating gates of all the cell transistors within the selected cell block so that information of the cell transistors can be erased. At this time, the first through n-th word driver transistors WDT1 , WDT2, WDT3, . . . , and WDTn of the block driver 310, which controls the unselected cell block, should be turned off. As described in FIGS. 3 and 4, however, one or more word driver transistors of the block driver 310, for example, the first and third word driver transistors WDT1 and WDT3, can exhibit deteriorating characteristics due to electrical stress while the program operation is being performed a predetermined number of times or more. As a result, even if a voltage of 0 volts is applied to the driver control line DCL of the block driver 310, the first and third word driver transistors WDT1 and WDT3 are slightly turned on. Consequently, a voltage of or in vicinity of 0 volts is applied to the first and third word lines WL1 and WL3 of the unselected cell block, thereby erasing information stored in the cell transistors which are connected to the first and third word lines WL1 and WL3. In this case, the sub-threshold leakage current of the ground driver transistor GDT does not directly cause errors in the erase operation.
To solve the above problems, it is a first object of the present invention to provide a NAND-type flash memory device and a method of operating the same, for minimizing a gate bias which is applied to the driver transistors of a block driver connected to a cell block including selected cell transistors when selectively programming the desired cell transistors.
It is a second object of the present invention to provide a NAND-type flash memory device and a method of operating the same, for improving the reliability of the driver transistors of a block driver.
In accordance with the invention, there is provided a NAND-type flash memory device including a cell array area, which has a plurality of cell blocks, and a row decoder which has a plurality of block drivers, a string control line, n word control lines and a ground control line, the plurality of block drivers being connected to the plurality of cell blocks, respectively. The string control line, n word control lines and a ground control line are connected to the plurality of block drivers. Each of the block drivers includes a string driver transistor, n word driver transistors and a ground driver transistor. The string driver transistor is interposed between the string select line of a cell block and the string control line. The n word driver transistors are interposed between the n word lines of the cell block and the n word control lines, respectively. The ground driver transistor is interposed between the ground select line of the cell block and the ground control line. Each block driver also includes a first driver control line, which is connected to the gate electrodes of the odd numbered word driver transistors among the n word driver transistors, and a second driver control line, which is connected to the gate electrodes of the even numbered word driver transistors among the n word driver transistors.
Accordingly, in each block driver, the odd numbered word driver transistors are controlled independently from the even numbered word driver transistors. In addition, each block driver may further include a third driver control line which is connected to the gate electrode of the string driver transistor and the gate electrode of the ground driver transistor. Alternatively, the gate electrode of the string driver transistor in each block driver may be connected to the first or second driver control line, and the gate electrode of the ground driver transistor in each block driver may also be connected to the first or second driver control line.
The plurality of cell blocks share m bit lines. Each of the cell blocks includes m strings connected to the m bit lines, respectively. Accordingly, a plurality of strings, the number of which is the same as the number of the cell blocks, are connected to each bit line. Each string includes a string select transistor, n cell transistors and a ground select transistor, which are sequentially connected to each bit line in series. Accordingly, the strings correspond to NAND strings. Each cell transistor has a stacked gate structure. That is, each cell transistor has a tunnel insulating film, a floating gate, an inter-gate dielectric film and a control gate electrode which are sequentially stacked on the channel region between the source region and the drain region.
Each cell block also includes a string select line, n word lines and a ground select line, which cross the m bit lines. The string select line in each cell block is connected to the gate electrode of the string select transistors of the m strings, and the ground select line is connected to the gate electrodes of the ground select transistors of the m strings. Similarly, the n word lines are connected to the control gate electrodes of the n cell transistors of each string.
Each block driver functions as a switch for selectively applying a desired voltage to the string select line, the n word lines and the ground select line of a cell block which is connected thereto. The source region and the drain region of the string driver transistor of each block driver are connected to the string control line and the string select line, respectively. The source region and the drain region of the ground driver transistor of each block driver are connected to the ground control line and the ground select line, respectively. Similarly, the source regions of the n word driver transistors of each block driver are connected to the n word control lines, and the drain regions of the n word driver transistors are connected to the n word lines.
As described above, according to the present invention, different voltages can be applied to the gate electrodes of the odd numbered word driver transistors and to the gate electrodes of the even numbered word driver transistors, among the n word driver transistors connected to the n word lines of each cell block one to one.
A method of operating, that is, programming, a NAND-type flash memory device having a structure as described above is performed after erasing a desired cell block or all cell blocks. That is, an erasing operation is performed such that all cell transistors in at least one cell block including at least one cell transistor to be programmed have a threshold voltage of lower than 0 volts, for example, about xe2x88x923 volts, before performing a programming operation.
In accordance with the programming method of the invention, one of the m bit lines is selected, and one of the plurality of strings which are connected to the selected bit line is selected. A first voltage higher than a program voltage is applied to one group of the group of gate electrodes of the odd numbered word driver transistors in a block driver connected to the selected string and the group of the gate electrodes of the even numbered word driver transistors in the block driver connected to the selected string. A second voltage, which is higher than a pass voltage and lower than the program voltage, is applied to the other group of the gate electrodes, to selectively program one of the n cell transistors of the selected string.
In one embodiment, the pass voltage is higher than a power voltage. In one embodiment, the first voltage is the program voltage plus xcex1, and the second voltage is the pass voltage plus xcex2. The voltage oxcex1 x is equal to or higher than a threshold voltage, which the word driver transistors have when a bulk bias corresponding to the program voltage is applied between the bulk region and the source region in each word driver transistor. The voltage xcex2 is equal to or higher than a threshold voltage, which the word driver transistors have when a bulk bias corresponding to the pass voltage is applied between the bulk region and the source region in each word driver transistor.
In one embodiment, the step of selecting one bit line is implemented by selecting and grounding one bit line among the m bit lines, and applying a program inhibition voltage, for example, a power voltage, to unselected bit lines among the m bit lines.
The step of selecting one string can be implemented by applying the power voltage and a voltage of 0 volts to the string control line and the ground control line, respectively, and turning on a string driver transistor and a ground driver transistor connected to one of the plurality of strings which are connected to the selected bit line in parallel.
The step of tunning on the string driver transistor and the ground driver transistor can be implemented by applying a third voltage higher than the power voltage to the gate electrode of the string driver transistor and to the gate electrode of the ground driver transistor. Preferably, the third voltage is lower than the program voltage. Most preferably, the third voltage is lower than the pass voltage and is the power voltage plus xcex3. The voltage xcex3 is equal to or higher than a threshold voltage, which the string driver transistor has when a bulk bias corresponding to the power voltage is applied between the bulk region and the source region in the string driver transistor. As a result, both the string driver transistor and the ground driver transistor are turned on. Consequently, the string select transistor of the selected string is turned on, and thus the channel region of the string select transistor comes to have the ground voltage applied to the selected bit line.
In another embodiment, the step of tunning on the string driver transistor and the ground driver transistor can be implemented by applying the first or second voltage to the gate electrode of the string driver transistor, and applying the first or second voltage to the gate electrode of the ground driver transistor. Since the first and second voltages are higher than the third voltage, the string driver transistor is turned on.
In the step of programming one cell transistor, one word control line among the n word control lines, for example, a word control line which is connected to one of the word driver transistors having the gate electrodes to which the first voltage is applied, is selected, and the program voltage is applied to the selected word control line. A voltage of 0 volts is applied to a pair of word control lines which are disposed at both sides of the selected word control line. The pass voltage is applied to remaining word control lines other than the selected word control line and the grounded pair of word control lines among the n word control lines. Accordingly, among the n cell transistors of the selected string, a cell transistor connected to the word control line to which the program voltage is applied is selectively programmed. The channel regions of the word driver transistors having the gate electrodes to which the first voltage is applied have the program voltage or the pass voltage. Accordingly, the maximum value of a gate bias, which is applied between the channel area and the gate electrode in each word driver transistor, is (VPGM+xcex1)xe2x88x92VPASS. The channel regions of the word driver transistors having the gate electrodes to which the first voltage is applied have a voltage of 0 volts or the pass voltage. Accordingly, the maximum value of a gate bias, which is applied between the channel area and the gate electrode in each word driver transistor, is VPASS+xcex2. Consequently, compared to conventional technology, a NAND-type flash memory device of the present invention can lower a gate bias which is applied to the word driver transistors during a programming operation. Therefore, the reliability of the word driver transistors can be improved, thereby decreasing errors occurring during an erasing operation.